Design and Optimization of GaN Nanowire FET for Direct Coupled FET Logic Circuits

Abstract The work reports a structural parameter optimization of GaN Nanowire FET for Direct Coupled FET Logic (DCFL) circuit applications. The device Ion/Ioff ratio of the E-Mode and D-Mode devices were ~ 108 and ~ 103, respectively. The device performance metrics extracted values are (i) SS: 94.14 mV/Dec. (E-Mode) and 96.80 mV/Dec. (D-Mode), (ii) DIBL: 31.58 mV/V (E-Mode) and 33.35 mV/V (D-Mode), (iii) gm: 1.5 µS (E-Mode) and 17.5 µS (D-Mode), and (iv) power consumption: 0.495 µW (E-Mode) and 11.8 µW (D-Mode). The E-Mode and D-mode devices can be obtained on the same chip with nanowire channel thickness variations which helps us to improve the overall circuit functionality.