Nanoscale Accumulated Body Si nMOSFETs

Narrow- and short-channel inversion-mode nMOSFETs with an accumulated body are experimentally demonstrated down to ${W} \times {L} = \textsf {17}$ -nm $\times37$ -nm scale. Accumulation of holes on the p-type body is achieved by applying a negative bias on an independently controlled p+ polysilicon side-gate structure surrounding the FET body. Affecting the channel from two sides, electrical characteristics of the transistor can be modified, especially the threshold voltage ( ${V} _{T}$ ). ${V} _{T}$ sensitivity to the side-gate bias ( ${V} _{\textsf {side}}$ ) shows a strong dependence on the device width for ${W} nm, exponentially increasing to above 1 V/V for ${W} = \textsf {17}$ nm. This sensitivity is significantly larger than what is predicted by 3-D Technology Computer Aided Design simulations. The devices exhibit very low leakage, good subthreshold slope, and improved drain-induced barrier lowering with the accumulation of the body.