New methodology of simulating pocket-implanted sub-0.18-μm CMOS

This paper presents a new approach to model the pocket implanted transistors for simulating sub-0.18 micrometer CMOS. The simulation approach presented in the prior publications for pocket implanted transistors has limitations in accurately matching the experimental Vt-rolloff and DIBL characteristics for gate lengths in the sub-0.18 micrometer regime. This is due to the fact that the pocket profile used in the prior simulator does not account for the 2-D boron redistribution effect caused by the source/drain extension implant (MDD). The new model incorporates two-dimensional redistribution of pocket caused by the drain extension implant. There are no additional modeling parameters added for the simulations when compared to the previously published model. The calibrated simulator with the new pocket model shows good agreement with the experimental data for 0.10 - 0.18 micrometer technology transistors.