An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments

A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures A-to-D architectures, compensating slope deviations due to technological/electrical reasons. Moreover, the calibration circuit shares the same analog circuits of the A-to-D converter, requiring only a small additional power budget and logic for the implementation. The calibration circuit has been validated, testing the overall A-to-D converter after the calibration. A 12 steps binary search is required to calibrate the A-to-D converter (about 2.5ms). This calibration circuit is able to guarantee an 11bits accuracy, in the worst case simulation corner. The technology used is a 65 nm CMOS. The clock frequency has been set to 20 MHz and the power consumption is about 400 μW.