New insights into 10nm FinFET BTI and its variation considering the local layout effects

In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized in 10nm compared with 14nm, the BTI and its variation show no obvious differences from the previous node. And this result is further confirmed by SRAM level reliability characterizations. In addition, the impacts of local layout effects on reliability are also investigated. Through Si data, BTI and its variation are not very sensitive to the layout effects which show within about 10% of the differences and the adopted structure for qualification can cover with all the different structures. Moreover, the results are also helpful for the accurate reliability modeling and circuit simulation.