SYSTEMATIC DESIGN AND EVALUATION OF RECONFIGURABLE ARITHMETIC COMPONENTS IN THE DEEP SUBMICRON DOMAIN

In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never stops. On the other hand, fabrication technology can not cover this demand with frequency increase and dimension shrinking only, as it has been done in the past. Reconfigurable computing is a new design paradigm that takes advantage of idle components or shared functionality between different algorithms, to maximize utilization and improve performance, based on efficient circuit switching interconnections. However, dense and fast switching interconnections bring power dissipation problems, which are more clear in the deep submicron domain. This paper, presents a systematic design methodology, handling performance, area and both dynamic and static power reduction optimizations in the ASIC domain, for a class of reconfigurable arithmetic components, which can be used as IPs in register-transfer level (RTL) and above RTL synthesis methodologies (electronic system level — ESL, high-level synthesis — HLS, IP-based). Both operand bitwidth and technology scaling are explored, showing that the overall proposed architecture offers clear advantages as device dimensions shrink.