A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and V OH Calibration in 20NM DRAM Process

A sub-0.85V, 6.4Gb/s TX-interleaved transceiver with fast wake-up time using 2-step charging control and a V OH calibration scheme is implemented using 20nm DRAM process. Adopting an interleaving scheme based on improved DRAM process, the proposed design operates at lowest supply voltage of 0.83V in DRAM process, and improves pin-efficiency by 30% compared with recent DRAM I/O interfaces. The fast wake-up time level shifter can achieve target switching voltage level without latency increase. And the leakage current by newly adopted transistors can be alleviated using a splitted power gating scheme.