Hole Mobilities of $\hbox{Si/Si}_{0.5}\hbox{Ge}_{0.5}$ Quantum-Well Transistor on SOI and Strained SOI

Hole mobilities of quantum-well p-MOSFETs on strained Si (sSi)/Si 0.5 Ge 0.5 /strained SOI (sSOI) and Si/Si 0.5 Ge 0.5 /SOI heterostructure substrates are investigated as a function of temperature. Ge interdiffusion during annealing in highly strained Si 0.5 Ge 0.5 on SOI is reduced by the growth of Si 0.5 Ge 0.5 layer on biaxially tensely strained SOI. As a result, the sSi/Si 0.5 Ge 0.5 /sSOI transistors showed significantly higher hole mobilities than the Si/Si 0.5 Ge 0.5 /SOI device at low temperatures.