Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing

The rapid growth in CMOS technology enables the technology of three-dimensional (3D) SoCs to be a promising approach for extending Moore's Law. Although the benefits supplied by 3D integration, managing test architecture design and reducing test cost are crucial challenges. Some powerful automatic test equipments (ATEs) that support different speed rate channels come into people's vision. In this paper, we propose a dual-speed TAM architecture optimization for 3D SoCs with hard dies, including a novel algorithm to minimize test time for both mid-bond and post-bond testing according to this new TAM architecture. Experimental results on ITC'02 SoC benchmark circuits show that our proposed scheme reduces total test time by around 35% on average compared with one baseline solution.