Design, Implementation, and Verification of a Data Acquisition System for the Prototypes of the Front-End Electronics of the PANDA Micro Vertex Detector

This paper describes the current status of the design, implementation, and test of a data acquisition (DAQ) system for the prototypes of the front-end electronics of the Antiproton Annihilation at Darmstadt ($\mathrm{\bar{P}ANDA}$) Micro Vertex Detector (MVD). The features of this DAQ, called Juelich Digital Readout System (JDRS), are driven by the requirements imposed by the physics program of the experiment, such as continuous data collection without external triggering. Flexibility and modularity are thus key points for this system, which is meant to operate during a test beam, as well as in a laboratory environment. The implementation of the system is based on an off-theshelf field-programmable gate array (FPGA) board. So far, two different application-specific integrated circuits (ASICs) have been successfully connected to the JDRS. Tests to establish the performance of the JDRS in terms of processing speed and reliability have been carried out and are still ongoing.