Low power, high-sensitivity clock recovery circuit for LF/HF RFID applications

This paper presents a fully integrated CMOS carrier clock recovery circuit for RFID applications. The architecture is based on a PMOS-input folded-cascode amplifier that combined with a modulator stage, present at conventional RFID transponders, achieves a good clock recovery performance even with a few mV at the antenna during modulation, allowing the transponder to communicate in a higher distance. Fabricated in a deep-submicron CMOS process, the circuit works with a 3 V power supply and delivers a 1 V peak-to-peak digital clock signal. Experimental data show that this circuit provides clock recovery with a 100 mV sensitivity (peak to peak) consuming only 260 nA of current.