A 7 bit 800MS/S SAR ADC with background offset calibration

This paper introduces a single-channel high-speed SAR ADC design. The new design uses asynchronous timing and split capacitor array to improve the ADC speed. It uses bottomplate sampling to improve the ADC linearity. A new comparator is designed to keep the capacitance at its gate constant over the bit cycling procedure so as to keep the comparator offset constant. Circuits are integrated in the comparator to calibrate its offset in the background. As a result, the ADC can achieve good SNDR A 7-bit 800MS/s SAR ADC is implemented in a 65nm CMOS process with the new techniques. Post-layout simulations show that the new ADC has competitive performance (42.3dB SNDR at Nyquist rate and 7.68mW power) compared to state-of-art designs. Our design achieves very low FoM (90 fJ/conv.-step).