Evaluation of Large L3 Caches Using TPC-H Trace Samples

In this chapter we evaluate the miss rates of four L3 cache architectures for small-scale multiprocessors. Eight processors are partitioned into 1, 2, 4, or 8 clusters with 8, 4, 2, or 1 processors, respectively. Each cluster has a large L3 cache, and the aggregate amount of L3 cache in each of the four architectures varies between 64 MB and 1 GB. The target of our evaluations is decision support systems. We use bus trace samples obtained during the execution of a 100 GB TPC-H on an 8-way multiprocessor. These 12 time samples were taken at one hour intervals during the first day of execution of TPC-H. Each sample contains 64 M bus references.