Investigation of Tunneling Current in $\hbox{SiO}_{2}/ \hbox{HfO}_{2}$ Gate Stacks for Flash Memory Applications

Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO 2 /HfO 2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO 2 is not suitable for use in SiO 2 /HfO 2 stacks for tunnel barrier engineering applications. The performance of SiO 2 /HfO 2 stacks improves with decreasing thickness of the HfO 2 layer. Mild (10%) O 2 /N 2 anneals do not significantly affect performance, although annealing above 600°C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO 2 /HfO 2 stacks.