A Compact DC I-V Model for ReRAM

In this work, a simple DC I-V model is developed for ReRAM devices. Different stages of a generic ReRAM operation such as forming of low resistance state (LRS), SET in forward and reverse applied-bias and RESET to high resistance state (HRS) are explicitly modeled with key independent parameters such as SET/RESET voltage and HRS/LRS resistance values. This approach of using key parameters as SPICE model input enables the device and circuit designers to come up with design guidelines for the final T-1R specifications from the READ/WRITE margin analysis. Based on Monte-Carlo simulations, the maximum allowable process variations can be estimated quickly and accurately, thus providing a standard design methodology for 1T-1R architectures.