3-5 GHz multifinger CMOS LNA using a simultaneous noise and impedance matching technique by a significant reduction of broadband impedance variation of metal–oxide–semiconductor field effect transistor

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two-dimensional contour plot-based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain (S 21), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG-input-matched LNA, the post-layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS-input-matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.