A linear model for high-level delay estimation in VDSM on-chip interconnects

This work introduces a linear model for high-level prediction of delay in capacitively and inductively coupled very deep sub-micron (VDSM) on-chip interconnects. The proposed estimation model approximates the signal delay as a linear combination of the contributions induced by each other aggressor line. It accurately predicts the delay in both capacitively and inductively coupled lines for the complete set of the switching patterns, and not only for the worst case, as in previous works. Therefore, it is suitable for fast yet efficient high-level analysis of bus encoding schemes envisaging delay minimisation. The accuracy of the model has been assessed by means of extensive experiments using 3D field solvers and SPICE simulations.