A 16 mW, 120 dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm 2 .