Radiation hardness test and characterization of a low-noise front-end readout ASIC in 180 nm CMOS technology for space X-ray survey

Abstract In this paper, we present total-ionization dose (TID) radiation hardness test methods and the analysis of experimental results of a low-noise front-end ASIC dedicated to CZT and/or Si-PIN detectors for X-ray surveys in space. A six-channel front-end readout prototype chip is designed and implemented in 180 nm CMOS process. The topology, circuit descriptions, and radiation-hardened-by-design techniques are firstly presented. Secondly, the radiation test apparatus, radiation test conditions, DUTs, test boards and the radiation test flow are introduced. Then, experimental results including the electrical performance before irradiation, key parameters including leakage current, gain, nonlinearity, and ENC slope after TID radiation are described and discussed. With the accumulation of the total dose, the leakage current is suppressed; the gain and the nonlinearity vary slightly; the noise performance is degraded. After the annealing process, the ASIC operates normally. However, the noise performance is degenerated. The ENC slope is twice than that before irradiation. It can be concluded that the proposed ASIC can resist total dose of 200 krad (Si) according to the radiation hardness assessment.