Investigation of back gate interface states by drain current hysteresis in PD-SOI n-MOSFETs

Abstract The hysteresis characteristics of the drain current in PD-SOI n-MOSFETs are examined at different back gate voltages ( V BG ) and temperatures. The relationship between the hysteresis and the back gate interface states is also discussed. The I D hysteresis, which is defined as the difference of I D for V FG swept up and down, showed both positive (1st) and negative (2nd) peaks at V FG around 0.6 and 1.1 V, respectively. The I D hysteresis depends on the back gate voltage. Both the 1st and 2nd peak heights of the I D hysteresis decrease with increasing temperature. This result indicates the lowering of the built-in potential of the source-body junction at high temperature. The activation energies for decreasing I D hysteresis are compared for different V BG conditions.