A Low-Power Optimization Method for Memory and Its Application

A low-power optimization method for memory was proposed based on folding structure and data packaging.In a given VLSI system,when read and write addresses of the memory changes mainly in accordance with the natural order,the proposed method could be used to realize low-power optimization by reducing memory access.Analysis based on SMIC 0.13 μm process showed that power consumption of the memory was reduced by about 50% only at the expense of a small area.Based on this method,a low power LDPC decoder was designed for CMMB system.It has been demonstrated that power consumption of the LDPC decoder was reduced by 21% and 33% with only 1.2% and 6.0% area increase,respectively.