Analytic Model of Spalling Technique for Thickness-Controlled Separation of Single-Crystalline Semiconductor Layers

Abstract Thickness-controlled separation of a thin layer of single-crystalline semiconductors from its bulk substrate is being developed for co-integration of compound semiconductors with silicon-based integrated-circuit (IC) chips and fabrication of high-performance flexible devices. Recently, a controlled spalling technique that can mechanically separate single-crystalline semiconductor layers has been actively demonstrated because of the process simplicity and the less limitation in materials. Here, we developed an analytic model that can precisely estimate the spalling depth. In this model, the spalling depth was calculated from the thermodynamic equilibrium condition in which total strain energy accumlated in a separated layer is balanced with the crystal binding energy. We empirically investigated the dependence of the spalling depth on the stressor layer thickness and stress, and we compared the empirical results with the suggested analytic model. We also verified that the crack initiation angle of the spalling process is determined by the binding energy contrast in the main crystal orientations in the semiconductor.