Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moore's Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET [1–4], in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape [5]. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.