Finite-state Machine

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Real-time computing , Discrete mathematics , Computer Science , Algorithm , Programming language

Child Topic:

Karnaugh map , Causal loop diagram , Boundary scan , Numerically controlled oscillator , Raft , Scan chain , Virtual synchrony , UML tool , Basis path testing , Quantum finite automata , Terminal and nonterminal symbols , Modified Frequency Modulation , Ninety-ninety rule , Moore machine , Decision table , Programmable logic device , De Bruijn graph , Lexical grammar , K shortest path routing , Myhill–Nerode theorem , Syntactic monoid , User Datagram Protocol , Black-box testing , Transmission Control Protocol , Context-free grammar , Simple LR parser , Adder , DFA minimization , Boolean circuit , State transition table , Truth function , Context-sensitive language , Perl Compatible Regular Expressions , Unary numeral system , Formal grammar , Control unit , Subtractor , Reo Coordination Language , DEVS , Post correspondence problem , Runt pulse , Ring counter , One-hot , Stochastic Petri net , Serial binary adder , High impedance , Race condition , Sequential logic , NMOS logic , One instruction set computer , Key , State machine replication , Concatenation , Synchronous circuit , LL grammar , GLR parser , Pin compatibility , Recursive language , Greibach normal form , Functional completeness , Classification Tree Method , Paxos , Chomsky normal form , Indexed grammar , Discrete system , Clock domain crossing , Parsing expression grammar , Recursive descent parser , Kleene star , Compiler-compiler , Package , Abstract state machines , Backus–Naur Form , Boundary-value analysis , Embedded pushdown automaton , Pattern matching , Event loop , Object modeling language , Mutation testing , UML state machine , Deterministic automaton , Legacy code , CTL* , Deployment diagram , Linear bounded automaton , Noise margin , Class-responsibility-collaboration card , Linear temporal logic , Emitter-coupled logic , Top-down parsing , Bottom-up parsing , Control store , Resource Reservation Protocol , Modified condition/decision coverage , Context-free language , Kahn process networks , Regular language , Context-sensitive grammar , Code generation , Relay logic , Asynchronous system , Cam timer , Contamination delay , PMOS logic , Flowchart , Combinational logic , Kripke structure , LL parser , Diode–transistor logic , Digital electronics , NOR gate , Logic gate , Extended finite-state machine , Augmented Backus–Naur Form , Stochastic context-free grammar , State pattern , Fan-out , Deterministic pushdown automaton , Asynchronous circuit , Programmable Array Logic , Deterministic context-free language , Multitape Turing machine , Class diagram , Directed acyclic word graph , Propagation delay , Alphabet , Finite state transducer , Implication table , Intelligent Network , Quality of results , Finite state machine with datapath , Nested word , Erasable programmable logic device , Gray code , Analogue electronics , Regular tree grammar , Fibonacci word , Object Constraint Language , Indexed language , Ambiguous grammar , Partial word , 7400 series , Decoder , Quine–McCluskey algorithm , Object diagram , Powerset construction , Most significant bit , Clock skew , There's more than one way to do it , Basic Rate Interface , Mealy machine , Second source , Chomsky hierarchy , LALR parser , Formal language , Espresso heuristic logic minimizer , Probabilistic automaton , Register-transfer level , Parallel random-access machine , X-machine , Empty string , Equivalence partitioning , NAND gate , Orthogonal array testing , Discrete event dynamic system , LR parser , HostLink Protocol , Model-based testing , Fault model , Programmable logic array , Deterministic finite automaton , Dynamic testing , Least significant bit , Object-modeling technique , Dyck language , Partial order reduction , System under test , Signal edge , Saturation arithmetic , Inverter , Reversible computing , Activity diagram , Hardware register , Booch method , Transistor–transistor logic , Integer overflow , String operations , Test suite , Pumping lemma for regular languages , Lexical analysis , Reactive system , Memory address register , Core dump , Tag system , ReDoS , Regular expression , Logic redundancy , Unified Modeling Language , Joint Test Action Group , Three-state logic , Nondeterministic finite automaton , Hazard , Shlaer–Mellor method , Clock gating , Pushdown automaton , ω-automaton , Circuit minimization for Boolean functions , Automata theory , Top-down parsing language , 4000 series , Systems Modeling Language , State , Message sequence chart , Implicant , Augmented transition network , Conceptual model , L , XML-RPC , Resistor–transistor logic , Model-driven architecture , Shift register , Element distinctness problem , Unrestricted grammar , Abstract family of languages , Turing machine , Petri net , Code coverage , Decision tree model , Truth table , C string handling , NOR logic , Grammar induction , OR gate , Open collector , Büchi automaton , XOR gate , Risk-based testing , Pull-up resistor , Multiple-emitter transistor , Canonical normal form , Computation tree logic , Timed automaton , Certificate , Logic level , Logic analyzer , Recursively enumerable language , AND gate , State diagram , Language construct , Regular grammar , Gbcast , Virtual finite-state machine

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