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Jose Ricardo Cardenas Valdez
Jose Ricardo Cardenas Valdez
Detector
Field-programmable gate array
VHDL
Control theory
Phase (waves)
2
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A Crest Factor Reduction Technique for LTE Signals with Target Relaxation in Power Amplifier Linearization.
2022
Sensors
Jose Ricardo Cardenas Valdez
José Alejandro Galaviz Aguilar
Cesar Vargas Rosales
Everardo Inzunza González
Leonardo Flores Hernandez
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FPGA-based design and implementation of a phase detector to correct the I/Q imbalance
2015
ROPEC | IEEE International Autumn Meeting on Power, Electronics and Computing
Thaimi Niubo-Aleman
Jose Ricardo Cardenas Valdez
J. A. Galaviz-Aguilar
J. Apolinar Reynoso-Hernández
M J Garcia-Ortega
J. C. Nunez-Perez
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