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Yoshihide Ajioka
Yoshihide Ajioka
Renesas Electronics
Electronic engineering
Interconnection
Capacitance
Differential capacitance
Parasitic capacitance
4
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24
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Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
2004
IEEE Transactions on Electron Devices
Tatsuya Kunikiyo
Tetsuya Watanabe
Toshiki Kanamoto
Hironobu Asazato
Mitsutoshi Shirota
Katsumi Eikyu
Yoshihide Ajioka
Hiroshi Makino
Kiyoshi Ishikawa
Shuhei Iwade
Yasuo Inoue
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Citations (14)
Symbolic Layout System: Application Results and Functional Improvements
1987
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Masayuki Terai
Yoshihide Ajioka
Tomoyoshi Noda
Masaru Ozaki
T Umeki
Koji Sato
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