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Kao-Chi Lee
Kao-Chi Lee
National Chiao Tung University
Electronic engineering
Computer science
Speedup
Logic gate
Binary search algorithm
4
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5
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A Model-Based-Random-Forest Framework for Predicting $V_{t}$ Mean and Variance Based on Parallel $I_{d}$ Measurement
2018
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Chien-Hsueh Lin
Chih-Ying Tsai
Kao-Chi Lee
Sung-Chu Yu
Wen-Rong Liau
Alex Hou
Ying-Yen Chen
Chun-Yi Kuo
Jih-Nung Lee
Mango Chia-Tso Chao
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Fast WAT test structure for measuring Vt variance based on latch-based comparators
2017
VTS | VLSI Test Symposium
Kao-Chi Lee
Kai-Chiang Wu
Chih-Ying Tsai
Mango Chia-Tso Chao
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ラッチベースコンパレータに基づく測定Vt分散のための高速WAT試験構造【Powered by NICT】
2017
Kao-Chi Lee
Kai-Chiang Wu
Chih-Ying Tsai
Chao Mango Chia-Tso
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Predicting Vt mean and variance from parallel Id measurement with model-fitting technique
2016
VTS | VLSI Test Symposium
Chih-Ying Tsai
Kao-Chi Lee
Chien-Hsueh Lin
Sung-Chu Yu
Wen-Rong Liau
Alex Hou
Ying-Yen Chen
Chun-Yi Kuo
Jih-Nung Lee
Mango Chia-Tso Chao
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Citations (4)
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