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Frank Verdico
Frank Verdico
Intel
Computer science
Electronic engineering
Clock domain crossing
Voltage regulator
Power supply rejection ratio
3
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16
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A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS
2018
A-SSCC | Asian Solid-State Circuits Conference
Shenggao Li
Fulvio Spagna
Ji Chen
Xiaoqing Wang
Luke Tong
Sujatha Gowder
Wenyan Jia
Roan M. Nicholson
Sitaraman V. Iyer
Rui Song
Lily Li
Meng-hung Chen
Amanda Tran
Michael De Vita
Deepar Govindrajan
Marcus Pasquarella
Dave Bradley
Frank Verdico
Matt Duwe
Eric M. Lee
Michelle Wigton
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Dynamic frequency-switching clock system on a quad-core Itanium® processor
2009
ISSCC | International Solid-State Circuits Conference
Andrew Allen
Jay Desai
Frank Verdico
Ferd Anderson
David Mulvihill
Dan Krueger
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Citations (15)
3.4 Dynamic Frequency-Switching Clock System on A
2009
Quad-Core Itanium
Andrew Allen
Jay Desai
Frank Verdico
Ferd Anderson
David Mulvihill
Dan Krueger
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