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M. Kondo
M. Kondo
Keio University
Electronic circuit
Microcontroller
Parallel computing
Combinational logic
Chip
4
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A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS
2011
Nobuyuki Ozaki
Yoshihiro Yasuda
Yoshiki Saito
Daisuke Ikebuchi
Masayuki Kimura
Hideharu Amano
H. Nakamura
Kimiyoshi Usami
M. Namiki
M. Kondo
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Geyser-2: the second prototype CPU with fine-grained run-time power gating
2011
ASP-DAC | Asia and South Pacific Design Automation Conference
L. Zhao
D. Ikebuchi
Y. Saito
M. Kamata
N. Seki
Y. Kojima
H. Amano
S. Koyama
T. Hashida
Y. Umahashi
D. Masuda
Kazuoki Usami
K. Kimura
M. Namiki
S Takeda
H. Nakamura
M. Kondo
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Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating
2010
ASP-DAC | Asia and South Pacific Design Automation Conference
D. Ikebuchi
N. Seki
Y. Kojima
M. Kamata
L. Zhao
H. Amano
T. Shirai
S. Koyama
T. Hashida
Y. Umahashi
H. Masuda
Kazuoki Usami
S Takeda
H. Nakamura
M. Namiki
M. Kondo
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Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating
2010
ASP-DAC | Asia and South Pacific Design Automation Conference
D. Ikebuchi
N. Seki
Y. Kojima
M. Kamata
L. Zhao
H. Amano
T. Shirai
S. Koyama
T. Hashida
Y. Umahashi
H. Masuda
Kazuoki Usami
S Takeda
H. Nakamura
M. Namiki
M. Kondo
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