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Dihang Yang
Dihang Yang
University of California, Los Angeles
Computer science
Electronic engineering
Electrical engineering
Phase-locked loop
Quantization (signal processing)
4
Papers
8
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0
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A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM.
2022
ISSCC | International Symposium on Security in Computing and Communication
Dihang Yang
David Murphy
Hooman Darabi
Arya Behzad
Asad A. Abidi
Stephen Au
Sraavan R. Mundlapudi
Kejian Shi
Weiyu Leng
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A Multi-loop Calibration-free Phase-locked Loop (PLL) for Wideband Clock Generation
2019
Dihang Yang
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16.6 A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fs rms Jitter and-70dBc Fractional Spurs
2019
ISSCC | International Solid-State Circuits Conference
Dihang Yang
Asad A. Abidi
Hooman Darabi
Hao Xu
David Murphy
Hao Wu
Zhaowen Wang
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A distance-immune low-power 4-Mbps inductively-coupled bidirectional data link
2017
VLSIC | Symposium on VLSI Circuits
Alireza Yousefi
Dihang Yang
Asad A. Abidi
Dejan Markovic
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Citations (3)
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