Old Web
English
Sign In
Acemap
>
authorDetail
>
Y. Koishikawa
Y. Koishikawa
Electronic engineering
Engineering
Electrical engineering
CMOS
High voltage
2
Papers
14
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (2)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
A 1.9-pm2 Loadless CMOS Four-Transistor SRAM Cell in a 0.18-pm Logic Techinology
1998
K. Noda
K Matsui
Kiyotaka Imai
K. Inoue
K. Tokashiki
H. Kawamoto
K. Yoshida
Koichi Takeda
N. Nakamura
Takeshi Kimura
H. Toyoshima
Y. Koishikawa
S. Maruyama
T Saitoh
Show All
Source
Cite
Save
Citations (5)
Double DESURF device technology for power ICs
1994
Nec Research & Development
Y. Koishikawa
M. Takahashi
H. Yanagigawa
T. Kuriyama
Show All
Source
Cite
Save
Citations (9)
1