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José Ricardo Cárdenas-Valdez

Instituto Politécnico Nacional

27

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139

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Implementing a Chaotic Cryptosystem by Performing Parallel Computing on Embedded Systems with Multiprocessors

2019 Entropy
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Implementing a chaotic cryptosystem in a 64-bit embedded system by using multiple-precision arithmetic

2019 Nonlinear Dynamics
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Comparison of a genetic programming approach with ANFIS for power amplifier behavioral modeling and FPGA implementation

2019 SOCO | Soft Computing
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FPGA-Based Emulation of Sequential Least Squares for Coefficient Extraction of RF Power Amplifiers

2018 ICM | International Conference on Mechatronics
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FPGA-based Chaotic Cryptosystem by Using Voice Recognition as Access Key

2018 Electronics
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Development and implementation of a fish counter by using an embedded system

2018 Computers and Electronics in Agriculture
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DESIGN AND FABRICATION OF A 64-QAM MODULATOR FOR ANALYSIS OF SIGNALS BETWEEN STAGES

2018
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Coefficients Estimation of MPM Through LSE, ORLS and SLS for RF-PA Modeling and DPD

2018
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METODOLOGÍA PARA LA IMPLEMENTACIÓN DEL MPM EN VHDL Y LA EMULACIÓN DE AMPLIFICADORES DE POTENCIA EN UNA TARJETA FPGA

2018
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Comparison of Two Methods for I/Q Imbalance Compensation Applied in RF Power Amplifiers

2017
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