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Kazunori Kakehi
Kazunori Kakehi
Toshiba
Electronic engineering
Engineering
Electrical engineering
Logic gate
Leakage (electronics)
3
Papers
32
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Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor
2012
IEDM | International Electron Devices Meeting
Yuji Kitamura
Hirotoshi Aikawa
Kazunori Kakehi
T. Yousyou
Kazuo Eda
Takashi Minami
S. Uya
Y. Takegawa
Hiroaki Yamashita
Yohichi Kohyama
Tokiko Asami
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An efficient manufacturing technique based on process compact model to reduce characteristic variation beyond process limit for 40 nm node mass production
2011
VLSIT | Symposium on VLSI Technology
Kazunori Kakehi
Hisanori Aikawa
T. Tadokoro
H. Eguchi
T. Hirayu
H. Yoshimura
Tetsuya Asami
K. Ishimaru
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Comprehensive study of systematic and random variation in Gate-Induced Drain Leakage for LSTP applications
2011
VLSIT | Symposium on VLSI Technology
S. Shimizu
Hisanori Aikawa
Shintaro Okamoto
Kazunori Kakehi
K. Ohsawa
H. Yoshimura
Tetsuya Asami
K. Ishimaru
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Citations (4)
1