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Jeehoon Han
Jeehoon Han
Samsung
Electronic engineering
NAND gate
Lithography
Multiple patterning
Flash memory
3
Papers
13
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0
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Comparison of double patterning technologies in NAND flash memory with sub-30nm node
2009
ESSDERC | European Solid-State Device Research Conference
Byungjoon Hwang
Jeehoon Han
Myeong-cheol Kim
Sung-Gon Jung
Nam-su Lim
So-wi Jin
Yong-Sik Yim
Dong-Hwa Kwak
Jae-Kwan Park
Jung Dal Choi
Kinam Kim
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Citations (4)
Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash
2008
ASMC | Advanced Semiconductor Manufacturing Conference
Byungjoon Hwang
Nam-su Lim
Jang-Ho Park
So-wi Jin
Minjeong Kim
Jaesuk Jung
Byungho Kwon
Jong-Won Hong
Jeehoon Han
Dong-Hwa Kwak
Jae-Kwan Park
Jung-Dai Choi
Won-Seong Lee
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Citations (7)
A Critical Failure Source in 65nm-MLC NOR Flash Memory Incorporating Co-Salicidation Process
2006
IIRW | International Integrated Reliability Workshop
Jeehoon Han
Bongyong Lee
Jungin Han
Wookhyun Kwon
Chaemyung Chang
Sang-pil Sim
Chan-Kwang Park
Kinam Kim
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Citations (2)
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