Old Web
English
Sign In
Acemap
>
authorDetail
>
Yude Liou
Yude Liou
Electronic engineering
Computer science
Electrical engineering
Voltage
Integrated circuit layout
2
Papers
76
Citations
0.00
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (2)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
Universal-V/sub dd/ 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell
2001
ISSCC | International Solid-State Circuits Conference
Kenichi Osada
Jinuk Luke Shin
Masood Khan
Yude Liou
Karl L. Wang
Kenichi Shoji
Kenichi Kuroda
Shuji Ikeda
Koichiro Ishibashi
Show All
Source
Cite
Save
Citations (76)
Voltage-Adapted Timing-Generation Scheme and a Lithographical-Symmetric Cell
2001
Kenichi Osada
Jinuk Luke Shin
Masood Khan
Yude Liou
Karl L. Wang
Kenichi Shoji
Kenichi Kuroda
Shuji Ikeda
Koichiro Ishibashi
Show All
Source
Cite
Save
Citations (0)
1