Old Web
English
Sign In
Acemap
>
authorDetail
>
Hirayu
Hirayu
Limit (mathematics)
Topology
Process control
Logic gate
Etching
1
Papers
0
Citations
0
KQI
Citation Trend
Filter By
Interval:
1900~2024
1900
2024
Author
Papers (1)
Sort By
Default
Most Recent
Most Early
Most Citation
No data
Journal
Conference
Others
An efficient manufacturing technique based on process compact model to reduce characteristic variation beyond process limit for 40 nm node mass production
2011
VLSIT | Symposium on VLSI Technology
Kakehi
Aikawa
Tadokoro
Eguchi
Hirayu
Yoshimura
Asami
Ishimaru
Show All
Source
Cite
Save
Citations (0)
1