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E. Stinzianni
E. Stinzianni
SEMATECH
Electronic engineering
Electrical resistivity and conductivity
Wafer
Surface roughness
Sheet resistance
2
Papers
10
Citations
0
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Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure
2014
VLSIT | Symposium on VLSI Technology
Kausik Majumdar
Robert D. Clark
T. Ngai
Kandabara Tapily
Steve Consiglio
E. Bersch
K. Matthews
E. Stinzianni
Ying Trickett
G.Nakamura
Cory Wajda
Gert Leusink
Hyuncher Chong
V. Kaushik
Joseph C. Woicik
C. Hobbs
P. D. Kirsch
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Citations (7)
Ultra low contact resistivity ( −8 Ω-cm 2 ) to In 0.53 Ga 0.47 As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates
2014
IEDM | International Electron Devices Meeting
Rinus T. P. Lee
Y. Ohsawa
C. Huffman
Ying Trickett
G.Nakamura
C. Hatem
K.V. Rao
F. Khaja
Rong Lin
K. Matthews
Kathleen Dunn
Anders Jensen
T. Karpowicz
Peter Folmer Nielsen
E. Stinzianni
A. Cordes
P.Y. Hung
Dae-Hyun Kim
R.J.W. Hill
Wei-Yip Loh
C. Hobbs
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Citations (3)
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