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M. Nashner
M. Nashner
Intel
Materials science
Electronic engineering
Wafer
Interconnection
Electromigration
2
Papers
17
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A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low-k ILD interconnects on 300 mm wafers
2004
IITC | International Interconnect Technology Conference
C-H Jan
Nidhi Anand
C. Allen
Jeffrey Bielefeld
M. Buehler
V. Chikamane
Kevin J. Fischer
K. Jain
J. Jeong
S. Klopcic
T. Marieb
B. Miner
P. Nguyen
A. Schmitz
M. Nashner
Tracey Scherban
B. Schroeder
C. Ward
R. Wu
K. Zawadzki
Scott E. Thompson
M. Bohr
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Citations (6)
90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology
2003
IITC | International Interconnect Technology Conference
C-H Jan
Jeffrey Bielefeld
M. Buehler
V. Chikamane
Kevin J. Fischer
T. Hepburn
Ankur Jain
J. Jeong
T. Kielty
S. Kook
T. Marieb
B. Miner
P. Nguyen
A. Schmitz
M. Nashner
Tracey Scherban
B. Schroeder
P.-H. Wang
R. Wu
J. Xu
K. Zawadzki
Scott E. Thompson
M. Bohr
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Citations (11)
1