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Walker J. Turner
Walker J. Turner
Nvidia
Computer science
Clock generator
Electronic engineering
Oscillation
Inverter
3
Papers
2
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0
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Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
2021
DATE | Design, Automation, and Test in Europe
Mingjie Liu
Walker J. Turner
George F. Kokai
Brucek Khailany
David Z. Pan
Haoxing Ren
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ParaGraph: layout parasitics and device parameter prediction using graph neural networks
2020
DAC | Design Automation Conference
Haoxing Ren
George F. Kokai
Walker J. Turner
Ting-Sheng Ku
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A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET
2019
CICC | Custom Integrated Circuits Conference
Sanquan Song
John W. Poulton
Xi Chen
Brian Zimmer
Stephen G. Tell
Walker J. Turner
Sudhir S. Kudva
Nikola Nedovic
John M. Wilson
C. Thomas Gray
William J. Dally
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