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S. Walstra
S. Walstra
Intel
Electronic engineering
Soft error
CMOS
Computer science
Leakage (electronics)
4
Papers
347
Citations
0.01
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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process
2004
IEEE Journal of Solid-state Circuits
Peter Hazucha
Tanay Karnik
S. Walstra
B. Bloechel
James W. Tschanz
J. Maiz
Krishnamurthy Soumyanath
Gregory E. Dermer
Siva G. Narendra
Vivek De
S. Borkar
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Citations (113)
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process
2003
CICC | Custom Integrated Circuits Conference
Peter Hazucha
Tanay Karnik
S. Walstra
B. Bloechel
James W. Tschanz
J. Maiz
Krishnamurthy Soumyanath
Gregory E. Dermer
Siva G. Narendra
Vivek De
Shekhar Borkar
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Citations (59)
Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation
2003
IEDM | International Electron Devices Meeting
Peter Hazucha
Tanay Karnik
J. Maiz
S. Walstra
B. Bloechel
James W. Tschanz
Gregory E. Dermer
S. Hareland
P. Armstrong
S. Borkar
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Citations (140)
Impact of CMOS Scaling and SOI on soft error rates of logic processes
2001
Symposium on VLSI Technology
Scott Hareland
Jose Maiz
M Alavi
K. Mistry
S. Walstra
Chenyun Dai
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Citations (35)
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