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M. Robillard
M. Robillard
IBM
Computer science
Parallel computing
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A 2 ns zero wait state, 32 kB semi-associative L1 cache
1996
ISSCC | International Solid-State Circuits Conference
James J. Covino
D. Evans
Alan L. Roberts
M. Robillard
Jose Roriz Sousa
L. Temullo
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