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Shi-Yi Huang
Shi-Yi Huang
National Changhua University of Education
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Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs
2010
ASP-DAC | Asia and South Pacific Design Automation Conference
Tsung Yi Wu
Tzi-Wei Kao
Shi-Yi Huang
Tai Lun Li
How-Rern Lin
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