Selective epitaxial silicon growth in high aspect ratio contact on 70 nm node flash memory

Abstract Selective epitaxial growth (SEG) silicon as sacrificial layer is proposed to circumvent junction leakage ( I jun ) of bit line contact due to silicon substrate loss by high aspect ratio contact etching and spontaneous salicide formation. The result indicates that the appropriate SEG silicon in contact area significantly reduces I jun about three orders compared with no SEG silicon. In addition, the SEG method provides acceptable Kelvin contact resistance. Furthermore, during salicide formation, the consumed ratio of titanium to silicon is 0.7. It is confirmed that the feasible approach not only prevents from I jun deterioration but also adjusts contact resistance as well.