Scaling properties of the tunneling field effect transistor (TFET): Device and circuit

Abstract The scaling properties of the tunneling field effect transistor (TFET) are shown using standard 130 nm, 90 nm, and 65 nm CMOS process flows. For the different technology nodes the temperature dependence is presented. The device characteristic does not show degradation after a combined voltage and temperature cycle. It is shown that the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET. Experimental and simulation results are presented for mixed MOSFET/TFET circuits. The usage of the TFET does not cause delay degradation. The static power consumption and signal integrity are improved compared to the CMOS realization.