TIGRA: A Tightly Integrated Generic RISC-V Accelerator Interface

Field programmable gate array (FPGA) usage in HPC applications is growing with the need for energy efficient and application specific accelerators. Currently, FPGAs are used to accelerate algorithms using OpenCL with communication over PCIe (loosely coupled accelerators) or by modifying existing architectures to incorporate custom logic directly with a CPU (tightly coupled accelerators). However, only the loosely coupled paradigm is feasible to support a variety of acceleration. In this work, we introduce TIGRA, a zero latency interface designed to provide the benefit of tightly coupled accelerators without the developer burden of modifying the underlying architecture, which can enable their usage in HPC. TIGRA is demonstrated on the PicoRV32 processor with AES-128 bit encryption, posit arithmetic, and multiplication.