The Study on Evolvable Electrical Circuit Design Based on FPGA

The traditional evolutionary algorithm needs a lot of storage and handling ability in embedded logic project. Candidate’s solutions through the population, rather than the probability of vector of save memory and bite string processing. Concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm is proposed. This paper proposes a method of realizing the standard FPGA concise evolutionary algorithm with a few changes to improve search powers. A data flow and a block diagram design, this paper describes the show. Experimental results show that the requirements (logical block) need to implement, building processing speed and solution for the power evolvable hardware CEA.