Wafer Level Variability Improvement by Spatial Source/Drain Activation and Ion Implantation Super Scan for FinFET Technology

In this paper, CMOS wafer level ring oscillator frequency variability improvement >40% is demonstrated by either spatial source/drain activation or ion implantation super scan in FinFET technology. Yield improvement (up to 17%) is verified with better within wafer uniformity and with no intrinsic device performance degradation. Furthermore, the combination of super scan and spatial source/drain activation is suggested for optimized variability improvement benefits from individual device type uniformity tuning (super scan) and all device type uniformity tuning (from spatial S/D activation).