Highly relaible reference bitline bias designs for 64Mb and 128Mb chain FeRAMs

This paper presents highly reliable reference bitline bias designs for 64Mb and 128Mb chain FeRAM™. In order to compensate cell signal level shift of both "1" and "0" data inherent to ferroelectric material, the band-gap reference circuit with temperature coefficient trimmer and voltage generator with voltage trimmer using laser-fuses has been installed in 64Mb. This enhances tail-to-tail cell signal windows by ±22mV. Furthermore, in order to realize low voltage operation and compensate array operating voltage fluctuation as well as signal level shift with temperature variation, a new reference circuit called "elevator circuit" with trimmer using ferroelectric-fuses has been installed in 128Mb. This controls the dependency of reference voltage on operating temperature at low voltage 1.8V VDD and improves cell signal window by ±40mV and varies reference bitline bias with ifl.2V variation of array operating voltage VAA of 1.5V and improves cell signal windows by ±44mV.