Process integration of highly stable 1.25μm2 6T-SRAM cell with 45nm gate length triple gate transistors

Fully functional, highly stable 1.25μm 2 6T-SRAM cell with 45nm gate length Triple Gate transistors with excellent short-channel characteristics is demonstrated by using a planar layout of 90nm CMOS technology and deliberate optical proximity control. This is the smallest working cell size ever reported by adopting non-planar 3D structures. The cell demonstrates robust data storing capability, SNM values of more than 10% V DD , and clear read/write operations. Finally, the TDDB result of TG-transistors for gate oxide reliability assessment is reported for the first time.