Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

Abstract The use of co-sputtered Zirconium Silicon Oxide (Zr x Si 1−x O 2 ) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO 2 and ZrO 2 targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr x Si 1−x O 2 film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr 0.85 Si 0.15 O 2 dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ FE =51.7 cm 2 /Vs), and threshold voltage shift (ΔV TH =0.03 V).